А так нельзя. Будет исключение:
Control Transfer Instructions in Delay Slots and Forbidden Slots
In MIPS architectures prior to Release 6. if a control transfer instruction (CTI) is placed in a branch delay slot, the operation of both instructions is UNPREDICTABLE. In Release 6, if a CTI is placed in a branch delay slot or a compact branch forbidden slot, implementations are required to signal a Reserved Instruction exception. The following instructions are forbidden in branch delay slots and forbidden slots: any CTI, including branches and jumps, ERET, ERETNC, DERET, WAIT, and PAUSE. Their occurrence is required to signal a Reserved Instruction exception.